3-Port conference circuit for use in private automatic branch exchange

ABSTRACT

An improved conference technique whereby a number of channels in a telephone switching system employing pulse code modulation for transmission purposes are combined so that a number of subscribers may participate in a common telephone conversation. The conference circuit is provided with a continuous threshold to pass the primary signal and to exclude the reflection. It is only used in the selection process, and for conditions which do not provide the threshold being met, the previous speaker is retained.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates generally to transmission and switchingtechniques in telephone communication systems and, more particularly, toan improved conference technique whereby a number of channels in atelephone switching system employing pulse code modulation fortransmission purposes are combined so that a number of subscribers mayparticipate in a common telephone conversation. More particularly still,it relates to improvements in a three-port conference circuit of thetype disclosed in U.S. Pat. Nos. 3,699,264 and 4,007,338, both of whichare assigned to the same assignee as the present invention.

The present invention pertains to a three-port conference circuit foruse in a private automatic branch exchange similar to those unitsmanufactured by GTE Automatic Electric Incorporated and designatedGTD120. Circuitry with minimum modification could also be employed inclass five central offices that employ digital switching. Such telephonesystems employ a time switching network rather than the most prevalentearlier space divided switching network.

In time division switching networks a requirement exists to have sourcesof pulse code modulated voice samples associated with time slots. Thesetime slots allow the conference to sequentially receive the code foreach conferee. For the conference circuit to be effective, it must beable to recognize who the conferees are and, of course, who is notassociated with the conference. The circuitry must also be capable ofdistributing the conference speaker's code to each conferee. Informationof this sort is, of course, available in the telephone switching systemsreferred to above. It should be understood that only telephone switchingsystems employing pulse code modulation can use the circuitry of thepresent invention, and such circuitry interfaces with time divisionportions of such switching networks. Other codes (linear) could be used,but a modified decision algorithum would have to be used, since in thepresent disclosure, D2/D3 type coding is required.

2. Description of the Prior Art

An approach to the handling of pulse code modulated information andconference circuitry is taught by U.S. Pat. Nos. 3,699,264 and4,007,338, which are assigned to the same assignee as the presentinvention. In these noted patents, digital signals are not converted toanalog; rather binary words are compared from the participatingchannels, with the smallest binary numbers (this corresponds to thelargest analog signal) selected as the speaker. Various improvements inthe conference circuitry disclosed in these above-identified U.S.patents are disclosed in U.S. Pat. Nos. 4,002,981 and 4,054,755, both ofwhich are assigned to the same assignee as the present invention.

PCM conferencing as taught in the above-identified patents andapplication requires a source of pulse code modulated (PCM) coded voicesamples which have associated time slots. These time slots allow theconference to sequentially receive a code for each conferee. Theconference circuitry must be able to recognize who the conferees are andwho is not associated with the conference call. The conference circuit,in U.S. Pat. No. 4,007,338, then determines the loudest PCM voice sampleduring each PCM time frame, storing and outputing the selected PCM codeto all conferees. In other words, the binary words are compared from theparticipating channels, with the smallest binary members selected as thespeaker. These patents, therefore, utilize a minimum binary code toselect the speaker. This technique, called "instant speaker selection",for generating conferencing, however, is subject to degradation due tothe presence of idle channel noise and from non-talking conferees withindividual circuit DC offset voltage variations, as the speaker's audiosignal passes through the region and its PCM sample is at a high weightvalue. In addition, when two or more conference members are conversingsimultaneously, the conference circuit could alternately select a newspeaker for each time frame, thus degrading the quality of the speech ofconversing conferees.

In U.S. Pat. No. 4,022,981, an improved multi-port (beyond 3) conferencecircuit is disclosed utilizing a minimum binary code as employed in thecoding formats (D2 and D3) currently employed in pulse code modulatedtelephony. Generally, the method for choosing the speaker is to clearthe PCM buffers at time slot 94. Then the first conferee detected isloaded to a conferee register. The register is compared to a temporaryspeaker register. If the conferee code corresponds to a larger pulseamplitude modulated (PAM) sample (that is, it presents a smaller binaryvalue PCM code), the conferee code is loaded into the temporary speakerregister. Each new conferee code is loaded to the conferee register andthen compared to the temporary speaker register. If it is smaller inbinary value but larger in PAM, it is then transferred and becomes thenew temporary speaker. If not, it is written over when the next confereecode is loaded in. Finally, time slot 94 occurs and the temporaryspeaker register is transferred to a conference speaker register. Thisthen is the conference speaker for the next frame, and this registercontains the PCM code which all conferees except the speaker himselfwill receive. It will then be updated one frame later during the nextoccurrence of time slot 94.

In U.S. Pat. No. 4,054,755, a further improvement in the multi-portconference circuitry is provided. These improvements attempt to solvethe idle channel noise and circuit offset variation problem and, also,foreign signal protection (i.e., 60Hz signal longitudinally coupled tothe line). In the conference circuit, PCM samples are taken for eachconferee from the time switch and, via comparator circuits, a PCM sampleis sent to the conferee. Since the selected PCM sample is not determineduntil all samples are compared, a frame delay is required after whichall conferees except the selected conferee will receive the selected PCMsample from the previous frame. The selected conferee, in turn, receivesa null code (perfect idle channel). To minimize speech clipping orselecting noise, two circuits, a preliminary and a preferred speakerpreference circuit, are employed.

The preliminary preference circuit utilizes the identity of the previousselected speaker and after its PCM sample is compared, its binary weightis modified to the highest value of a corresponding curve segment. Thisis done by adding a bit between the segment and the step bits, allowingthe binary value to be decreased. This technique permits the conferencecircuit to hold on to the previous speaker if the incoming PCM samplesare in the same PCM segment or below in value.

The preferred speaker preference circuit functions when the magnitude ofthe present PCM sample exceeds the value of the preferred preferencecircuit threshold. When a speaker is selected for the succeeding frameand has a larger PAM (smaller PCM code) sample than the threshold, apreferred preference circuit creates a lower binary weight (apparentlylarger PAM) to the comparator, for the selected speaker, for a period ofone frame. This reduces speech clipping during that time when two ormore conferees are conversing simultaneously.

Neither the preliminary nor the preferred preference circuits alters theincoming or the outgoing PCM sample to the conferees; additional binaryweights are only presented to the comparison circuit to favor theprevious speaker.

SUMMARY OF THE INVENTION

The present invention is intended to provide improvements in theconference circuit taught in the above-referenced U.S. patents, toreduce or substantially eliminate the problem of high idle channel noiseresulting from always choosing the largest signal above null code (quietor absence of signal), the distortion of signals to the listeners anddistortion of the speaker side tone, and finally, difficulties fromforeign signals.

In experience with the previous inventions, it has been discovered thata major contribution to the speech quality degradation in digitalconferencing is due to signal reflections of the original signalcirculating and fighting for control of the conference. This problem ofsignal reflections could be solved by providing either reflectivesignals of low amplitude in relation to the primary or with no or verylittle phase shift. However, assuming present hybrid designs must bemaintained and termination impedance with wide variations will exist,the solution is shifted to the conference. To provide transmission ofonly the primary signal, a continuous threshold is established to passthe primary and exclude the reflection. It is only used in the selectionprocess. For conditions which do not provide the threshold being met,the previous speaker is retained. For three-port applications, thisrequires a memory for each time slot with logic to store the results ofthis decision and to be used for the same time slot during the nextframe. The memory then in combination with the threshold barrier allowsthe conference to lock to the speaker regardless of what he is sayinguntil someone else takes over. The idle channel noise is helped as onlyone source is sent so no amplification exists due to previous selectionsof the noise peaks of the sampled conferences. The side tone distortionis solved as only one signal will pass. The single speaker is improvedas long as the reflections are below the threshold. This, then, iscritical to system performance. If the threshold is too low, theproblems exist (threshold is null). If it is too high, the speakercannot enable the selection to the proper level. A long trunk connectionmay have quite a bit of loss, so a compromise in level must be made. Avariable threshold strapping is provided in the disclosure to providefor optimum applications.

In the previous three-port conference, the distortion to the listenerswas caused by the primary signal being compared to a reflected signalfrom a second listener. When the primary signal saw a zero crossing, thereflected signal, being out of phase (90° to 270° being the worse case),took over the conference, thus resulting in distortion. The speakerwould hear his own signal reflected from two listeners. If thelisteners' terminations caused a phase shift between each other, thespeaker's received signal would be also distorted giving him side tonedistortion. The threshold now allows the speaker's signal to crossthrough zero without loss of conference control, and the reflectedsignal (or noise) does not achieve the threshold, so only one isselected and held.

Multiple speaker operation still provides flip-flop operation and isvery rapid as compared to echo suppressor type flip-flopping or speakerphone operation. Thus, the loss of syllables is not heard, however, onemay notice the shift of background noise levels, especially if one has abackground signal like a radio.

The problem of foreign signals entering conference connections via trunkconnections is improved, and can be seen in low level variations onwhich the idle circuit signal or voice signal ride. The conferencerequires a common DC reference (null code) to judge the presence ofsignals. Trunk circuits which allow low frequency signals at low level(60Hz or its harmonics, for example) to be present have causeddistortion in the instant speaker case. This is because the largerspeaker is always chosen. With the conference circuit of the presentinvention, the constant switch is greatly reduced, by an improvedlocking method. The foreign signal is still present but it is notchopped up due to switching between idle channels.

The present invention also is applicable to a multiport conference andsuch an application of the principle (that of digital conferencing usingthreshold level comparison and last speaker memory) of the presentinvention is disclosed in a copending U.S. patent application, Ser. No.857,168, filed simultaneously herewith. The three-port conference isreally three two-port connections of a single conference, and the systemallows for 96 such two-port connections in memory. The multiple port(10, however, it is not necessary to limit the system to any number) isa single conference of 10 and has only one last speaker. The three-portdecision, since it is a choice of two sources for each of the threelisteners, needs no detection of the listener, while the ten-port needsto exclude the listener.

Generally in the three-port conference system, the conference circuitryincludes a delayed time slot address buffer, a last frame speakermemory, two threshold speaker comparators, and various combination logicgates. Also included are pull-up resistors and four straps to determinethe coded threshold level.

In operation, the previous saved data is read from the last framespeaker memory under control of the networks time slot counter, asbuffered by the delayed time slot address buffer. This previously-saveddata is available to the combinational logic, and the speaker A's fourhighest PCM bits are compared to the strapped threshold by one of thetwo threshold speaker comparators and its output indicates if thethreshold for speaker A is achieved. Likewise, the other one of the twothreshold speaker comparators indicates if speaker B's four highest bitsachieve the threshold. As only the larger of the two speakers can stilltake over, a signal A<B-1 generated by a seven bit PCM comparatorincluded within the network is provided to the combinational logic togate one of the thresholds to an OR gate. The output of this OR gateindicates that one of the two speakers has met the threshold and he isalso the largest during this frame. This condition disables the previousspeaker data, and also enables the gating of the speaker B conditioned.Since only a level is needed, speaker B is either the speaker or it mustbe speaker A. Then a second OR gate included within the combinationallogic indicates the results to the speaker flip-flop within the network.The output of the speaker flip-flop (after hold bits modification) isloaded into the last frame speaker memory for the next frame. Thisoperation occurs 96 times every frame, and provides 96 two-portdecisions. The network time slot counter generates addresses from 0 to95, and the last frame speaker memory uses only these locations eventhough it is implemented using a 256 × 1 RAM.

To permit synchronous operation with the network PCM time switch, timingcircuits are generated within the conference circuit which are derivedfrom the network clock.

The circuitry of the present invention is implemented using integratedcircuits of conventional design.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1 and 2 in combination, with FIG. 1 placed to the left of FIG. 2,comprise a functional and logic diagram of a conference circuitconnected to the switching network of a telephone system employing pulsecode modulation;

FIG. 1 comprises a diagram of the conference circuit; and

FIG. 2 comprises a diagram of the related portion of a switching systemnetwork.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Implementation of the present invention is accomplished by means ofcircuitry arranged in logic configuration as shown in FIGS. 1 and 2. Itshould be noted that detailed circuit configurations of such circuitryhave not been shown inasmuch as they do not form a portion of thepresent invention. It is well within the capability of those skilled inthe art to implement the required functional circuitry based on thestate-of-the-art technology. Commercially available logic circuitry isavailable to facilitate such implementation.

Referring now to FIG. 1, a conference circuit in accordance with thepresent invention is shown. The conference circuit includes a delayedtime slot address buffer 101 whose output is connected to a last framespeaker memory 102. The delayed time slot address buffer 101 is drivenby the network's time slot counter 209 and is clocked in response to QDpulses. The previously saved data in the last frame speaker memory 102is read therefrom under control of the time slot counter 209 as bufferedby the delayed time slot address buffer 101. This previously saved datais available to the combinational logic at the one input of the 2-inputNAND gate 114. The output of the speaker A register 215 is coupled tothe input of the threshold speaker comparator 103, and the speaker A'sfour highest PCM bits are compared to the strapped threshold. Likewise,the output of the speaker B register 216 is coupled to the thresholdspeaker comparator 104, and the speaker B's four highest PCM bits arecompared to the strapped threshold. If the threshold is achieved by thespeaker A, the threshold speaker comparator 103 provides an outputsignal TSPKA-1 to one input of the 2-input NAND gate 110.Correspondingly, if the speaker B achieves the threshold, the thresholdspeaker comparator 104 provides an output signal TSPKA-1 to one of theinputs of the 2-input NAND gate 111.

The outputs of the speaker A register 215 and the speaker B register 216also are coupled to the comparator 217 which compares the speaker A'sand speaker B's PCM signals and, if the speaker A's PCM signal is larger(less binary value) than the speaker B's PCM signal, provides a signalA<B-1 at its output to the other input of the NAND gate 110. This signallikewise is coupled through an inverter 112 to the input of the NANDgate 111. The outputs of the NAND gates 110 and 111 are both coupled tothe 2-input NAND gate 113 which functions as an OR for low signals. TheA<B-1 signal coupled to the NAND gates 110 and 111 gates one of thethreshold signals to the NAND gate 113, and its output indicates thatsomeone has met the threshold and also is the largest signal during thisframe during the present time slot. The output of the NAND gate 113 iscoupled through an inverter 116 to the input of the NAND gate 114, andis also directly coupled to the input of the NAND gate 115. The outputof the NAND gate 113 disables the previous speaker data at the gate 114,and also enables the speaker B conditioned to gate 115.

Since only a level is needed, speaker B is either the speaker or it mustbe speaker A. The outputs of the gates 114 and 115 are coupled to theinput of the NAND gate 117, which also functions as an OR for lowsignals, and this NAND gate 117 presents the results to the speakerflip-flop 218 of the network. The Q output of the speaker flip-flop 218is loaded into the last frame speaker memory 102 for the next frame.

The pull-up resistors 105-109 and the straps A-E provide a variablethreshold strapping arrangement, the results of which are coupled to thethreshold speaker comparators 103 and 104 to establish a thresholdvalue.

Referring now to FIG. 2, those portions of a switching network of a PABXemploying pulse coded modulated transmission techniques and digitalswitching on a time division basis which interfaces with the conferencecircuit of the present invention as shown. Such circuitry includes aninformation memory 201, a control A memory 202, a control B memory 203and a channel memory 204. Each memory has a capacity of 768 bits (96words of eight bits each). Information stored in the information memory201 is derived from the PCM outbus-1 which has connections toanalog-to-digital converters such as 225, 227 and 240 and also fromdigital tone circuitry 229. Control of the information memory 201 isfrom clock source 250 which drives time slot counter 209 and inputs to2:1 steering gate 210 and information gate through 2:1 steering gate 213whose inputs are connected to control A memory 202 and control B memory203 outputs. The output of steering gate 213 is inputed to the steeringgate 210. Information stored in the information memory 201 isdistributed during X and Y pulses, respectively, to speaker A register215 and speaker B register 216, both of which include outputs connectedto the input of 2:1 steering gate 219.

The speaker A register 215 and the speaker B register 216 have an outputconnection to the comparator 217 and to the threshold speakercomparators 103 and 104 of the conference circuit, respectively. Theoutput of comparator 217 indicates when the information stored inspeaker A register 215 is less than (PAM signal is larger than) theinformation stored in speaker B register 216; and is transmitted to thespeaker flip-flop 218 and to the gates 110 and 111 of the conferencecircuit. The speaker flip-flop 218 which is also controlled by HB-0 andHA-0 signals produces a speaker B output signal which is used to controlthe 2:1 gate circuit 219 and the last frame speaker memory 102 of theconference circuit. The output of the 2:1 gate 219 is connected to the2:1 steering gate 220. Control of gate 220 is via the NAND gate 221whose inputs are the HA-1 and HB-1 signals. The output from gate 220 isconnected to digital-to-analog circuit 226, 228 and 241 via gate 222.The channel memory 204 is driven by an early time slot counter 207 whichis reset earlier by decode gate 206 which decodes the time slot counter209. The 2:1 steering gate 208 then drives the channel memory to allowchannel identity stored in it which includes conferee identities to beoutputed to the channel enable register 214 and then to be distributedto channel enable circuits 250, 251 and 252. Pulse amplitude modulatedtransmission and receive buses provide connections between conferenceline circuits such as 224, which are gated by channel enable equipment250-252 via leads T-EN and R-EN.

Referring now to FIGS. 1 and 2 in combination, the operation beingdescribed assumes the switching network of FIG. 2 has been already setup by an associated central processor to allow for a conference of threeconferees. The method by which the call has been established is notimportant, and could result from such types of conference applicationsas progressive, meet me, or attendant (operator) conference. The typicalapplication is for two PABX lines and a trunk, or three lines. Twotrunks and a line are possible also. This is considered to be PBXthree-way calling conferences. The progressive, etc., are moremulti-party applications. In systems as previously referenced, suchdetermination is all software controlled and results in a networkconfiguration as shown in FIG. 2. The conferees may be served by lines,trunks, or might be a PBX attendant or operator.

In the network configuration shown, the conferees' equipment identity isstored in the channel memory 204. This location defines its associatedtime slot and allows signals stored in the channel enable register 216ahead of the channel enabling circuitry to generate, transmit enable(T-EN) and receive enable (R-EN) pulses to a conferee's circuit such as224. The control A memory 202 of the same time slot (i.e., same memoryword address of the channel memory 204 word with the identity) has thehold bit "off" and the first speaker's two-slot address. A control Bmemory then must have a hold bit also "off" and the second speaker'stime slot address. A 3-way connection will use three time slots of twospeakers each.

For purposes of the present discussion, assume the connectionsillustrated, in the information memory 201, the control A memory 202,the control B memory 203 and the channel memory 204. As illustrated, itindicates that line 1 (time slot 0) will hear both the PCM code of line2 (time slot 4) and the PCM code of trunk A (time slot 8). Likewise,line 2 (time slot 4) will hear both the PCM code of line 1 (time slot 0)and the PCM code of trunk A (time slot 8). Also, trunk A (time slot 8)will hear both the PCM code of line 1 (time slot 0) and the PCM code ofline 2 (time slot 4). These are the three conference operations betweenthe speaker A and the speaker B PCM codes accomplished every frame bythe conference circuitry of FIG. 1 which forms the 3-way conference.

Now, assume for this frame, that line 1 has said nothing and null code(perfect quiet signal, with no DC offset) is stored in location 0 of theinformation memory 201. Also, that line 2 has said something which wascoded above the threshold and that the trunk party has said somethingalso above the threshold but below that of line 2. This is only aninstant sample of code level, not actual measured tone level. The threedecision processes are as follows.

TIME SLOT 0

The speaker A is line 2 and the PCM code stored in the informationmemory 201 is coupled therefrom to the speaker A register 215 and to thethreshold speaker comparator 103. Since it was assumed that line 2 hassaid something which was coded above the threshold, the output (TSPKA-1)of the threshold speaker comparator 103 is true. The speaker B is trunkA and the stored PCM code is coupled from the information memory 201 tothe speaker B register 216 and to the threshold speaker comparator 104.Again, the output (TSPKB-1) of the threshold speaker comparator 104 willbe true, since it was assumed that the trunk party has said somethingalso above the threshold but below that of line 2. The output of thespeaker A register 215 and the speaker B register 216 also is coupled tothe comparator 217 and, assuming the conditions indicated, the output(A<B-1) of the comparator 217 is true (larger signals have smaller PCMcode values). Since both inputs to the gate 110 are true, the gate 110is enabled and its output goes low and is coupled to the one input ofthe NAND date 113. Since A<B-1 is true at this time, the NAND gate 111is not enabled and its output is high and is coupled to the NAND gate113. The output of the NAND gate 113 therefore is true and, as indicatedabove, this indicates that someone has met the threshold and is also thelargest speaker during this frame. The output of the NAND gate 113 iscoupled through the inverter 116 to the input of the NAND gate 114 thusdisabling the NAND gate 114, and hence the previous speaker data fromthe last frame speaker memory 102. The outputs of both the gates 113 and111 being high forces the output of the NAND gate 115 to go low.Accordingly, with the output of the gate 114 high, and that of gate 115being low, the output of the NAND gate 117 is then high which allows theselection of speaker A's PCM (select A PCM-1). The output (select APCM-1) of the NAND gate 117 is coupled to the select flip-flop 218 andsets it during QE. The Q output (SPKB-1) of the select flip-flop 218 isthen low and is coupled to the last frame speaker memory 102 wherein itis stored during QB of the next time slot (i.e., time slot 1). However,the delayed time slot address buffer 101 is still at count 0 since itwill not change until QD, so the results of the time slot 0 are storedin location 0. The output of the last frame speaker memory 102 invertsso a high will be read out during the next frame when time slot 0 nextoccurs.

TIME SLOT 4

During this time slot, the speaker A is line 1 and the speaker B istrunk A. Since, as assumed, line 1 has said nothing (perfect idlechannel) and the trunk A has said something above the threshold, whenthe outputs of the speaker A register 215 and the speaker B registers216 are coupled to the respective threshold speaker comparators 103 and104, the output of the threshold speaker comparator 103 (TSPKA-1) is lowand the output of the threshold speaker comparator 104 (TSPKB-1) ishigh. Also, since the speaker B is greater than speaker A, the output ofthe comparator 217 (A<B) is low. In this case, the output of the NANDgate 110 will be high, while the output of the NAND gate 312 will below. The output of the NAND gate 113 therefore again is high and theNAND gate 114 is disabled. Now, since the output of the NAND gate 111 islow, and the output of the NAND gate 113 is high, the output of the NANDgate 115 is forced to go high to, in turn, force the output of the NANDgate 117 (select A PCM) to go low. Since the output of the NAND gate 117is low, the select flip-flop 218 will be reset during QE, to selectspeaker B's PCM. The Q output (SPKB-1) of the select flip-flop 218 willbe high and stored in location 4 of the last frame speaker memory 102during QB of time slot 5.

TIME SLOT 8

During time slot 8, the speaker A is line 1 and the speaker B is line 2.Since it is assumed that line 1 said nothing and that line 2 had saidsomething which was coded above the threshold, when the outputs of thespeaker A register 215 and the speaker B register 216 are coupled to thethreshold speaker comparators 103 and 104, the output of the thresholdspeaker comparator 103 (TSPKA-1) is low, and the output of the thresholdspeaker comparator 104 (TSPKB-1) will be high. Also, speaker B isgreater than speaker A (less in code value) so the output of thecomparator 217 (A<B) will be low. The output of the NAND gate 110 willbe high and the output of the NAND gate 111 will be low, thus the outputof the NAND gate 113 is high and when coupled through the inverter 116to the NAND gate 114, again disables the latter. The output of the NANDgate 113 being high and the output of the NAND gate 111 being low againforces the output of the NAND gate 115 to go high. The output of theNAND gate 115 therefore forces the output of the NAND gate 117 (select APCM-1) to go low, to again select speaker B, via the select flip-flop218. Accordingly, since the Q output of the select flip flop 218(SPKB-1) is true, the latter is stored in location 8 of the last framespeaker memory 102 during the time slot 9.

Now, assume that line 1 again says nothing, that line 2 is below thethreshold and trunk A is above the threshold. During the followingframe, the sequence of events is as follows.

TIME SLOT 0

During time slot 0, the speaker A again is line 2 and the speaker Bagain is trunk A. Also, the output of the comparator 217 (A<B) is low.Accordingly, during this frame, the output of the threshold speakercomparator 103 (TSPKA) is low, while the output of the threshold speakercomparator 104 (TSPKB) is high. Therefore, since A<B is low, the outputof NAND gate 110 is high and the output of NAND gate 111 is low, thusforcing the output of NAND gate 113 to go high. This high after beingcoupled through the inverter 116 disables the NAND gate 114 and itsoutput goes high. The output of NAND gate 111 being low forces theoutput of NAND gate 115 to go high. Now, with both inputs to the NANDgate 117 being high, its output goes low, to select speaker B, via theselect flip-flop 218. Since the Q output of the select flip-flop 218(SPKB-1) is true, the latter is stored in location 0 of the last framespeaker memory 102 during the time slot 1.

TIME SLOT 4

During time slot 4, the speaker A again is line 2 and the speaker B istrunk A. Also, the output of the comparator 217 (A<B) is low. Therefore,the output of the threshold speaker comparator 103 is high, and that ofthe threshold speaker comparator 104 is low. This low upon being coupledto the NAND gate 115 forces its output to go high and when coupled tothe NAND gate 117 likewise forces its output to go low, so that speakerB is directly selected, via the speaker flip-flop 218. Speaker B then isstored in the last frame speaker memory 102.

TIME SLOT 8

During time slot 8, the speaker A is line 1 and the speaker B is line 2.Neither speaker achieves the threshold, and the output of comparator 217(A<B) is low. The output of the threshold speaker comparator 103therefore is high, and the output of the threshold speaker comparator104 is high. The NAND gate 113 through the inverter 116 provides a highto the NAND gate 114 to enable it, and a low to the NAND gate 115 todisable it. Now, the previous results are steered through the NAND gate114 to the NAND gate 117 to select speaker B, via the speaker flip-flop218. Speaker B again is stored in the last frame speaker memory 102.

Accordingly, it can be seen from the above description that theconference is made up of three decisions to update or reuse previousselections of speaker A or speaker B. A speaker can take over the otherspeaker, only by breaking through the established threshold level.Initially, it is a random selection, but as the first speaker speaks,the other two speakers flip to listen to him. The first speaker,however, hears one of the other two speakers depending on what is storedin the last frame speaker memory 102. His reflected signal will notchange this if the threshold level is above the value of the reflectedsignal.

Foreign signals are also locked in or out depending upon the lastspeaker to achieve the threshold. Idle channel noise selections are alsonot a result of the in value but, instead, depend on who has control ofeach conference time slot.

Multiple talkers achieve the threshold and rely on rapid selection ofspeech peaks in combination of the intersyllabic pauses.

We claim:
 1. In a pulse code modulated communication system, a pluralityof communication channels arranged on a multiplexed basis, a switchingsystem including a memory accessed by said communication channels, andcomparison means for comparing and indicating as an output thereof thelarger of two samples of information from a speaker A and a speaker Bcoupled to it, and a conference circuit connected to said memory and tosaid channels, said conference circuit comprising: a first thresholdspeaker comparator for comparing an established threshold level withsamples of information from said speaker A and indicating as an outputthereof that said samples of information from said speaker A exceedssaid established threshold level; a second threshold speaker comparatorfor comparing said established threshold level with samples ofinformation from said speaker B and indicating as an output thereof thatsaid samples of information from said speaker B exceeds said establishedthreshold value; and logic means comprising a plurality of gating means,said outputs from said first and second threshold speaker comparatorsand said comparison means being coupled to said logic means, said logicmeans being responsive to said outputs to select and to indicate to saidswitching system that one of said samples of information from saidspeaker A and speaker B that is larger in value when both said samplesof information from said speaker A and said speaker B exceed saidestablished threshold value.
 2. In a pulse code modulated communicationsystem, as claimed in claim 1, said conference circuit furthercomprising a last frame speaker memory for storing the identity of theone of said speakers A and B which was the active speaker during apreceding frame, the output of said last frame speaker memory beingcoupled to said logic means, said logic means further being responsiveto said output from said last frame speaker memory to select and toindicate to said switching system during the next succeeding frame theone of said speakers A and B selected as the active speaker during thepreceding frame when both said samples of information from said speakersA and B exceeds said established threshold level, whereby the activespeaker during a previous frame is selected and retained as the activespeaker during the next succeeding frame when both said samples ofinformation from said speakers A and B exceed the established thresholdlevel.
 3. In a pulse code modulated communication system, as claimed inclaim 2, said logic means further comprising gating means responsive tosaid output signals from said first and second threshold speakercomparators and from said last frame speaker memory to select and toindicate to said switching system the selection of the one of saidspeakers A and B that was the active speaker during the preceding framewhen neither one of said samples of information from said speakers A andB exceeds said established threshold level, whereby the same activespeaker during a previous frame is selected and retained as the activespeaker during the next succeeding frame when neither of said samples ofinformation from said speaker A nor B exceeds the established thresholdlevel.
 4. In a pulse code modulated communication system, as claimed inclaim 2, said logic means further comprising gating means responsive tosaid output signals from said first and second threshold comparatormeans and from said last frame speaker memory to select and to indicateto said switching system the selection of the one of said speakers A andB having the samples of information which exceeds said establishedthreshold level when only one of said speakers A and B has a sample ofinformation which exceeds said threshold level, whereby only the speakerhaving a sample of information that exceeds the threshold level isselected regardless of which speaker was the active speaker during apreceding frame.
 5. In a pulse code modulated communication system, asclaimed in claim 2, wherein said logic means comprises first gatingmeans coupled to said first and second threshold speaker comparators andresponsive thereto to indicate at the output thereof that one or both ofsaid speakers A and B has exceeded said established threshold level; anoutput gating means having an output indicating the selection of one ofsaid speakers A and B; a second gating means having inputs coupled tothe outputs of said last frame speaker memory and said first gatingmeans and an output coupled to an input of said output gating means,said second gating means normally being operative to couple the outputof said last frame speaker memory to said output gating means to operatethe latter to select and to indicate the selection of the one of saidspeakers A and B that was the active speaker during the preceding framein accordance with the output of said last frame speaker memory, saidsecond gating means being disabled by the output of said first gatingmeans indicating that the sample of information of one or both of saidspeakers A and B has exceeded said established threshold level, wherebythe selection of the speaker that was the active speaker during apreceding frame as the active speaker during the next succeeding frameis prevented when the sample of information of one or both of thespeakers A and B exceeds the established threshold level.
 6. In a pulsecode modulated communication system, as claimed in claim 5, wherein saidlogic means further comprises a third gating means responsive to theoutputs of said first threshold speaker comparator and said comparisonmeans to indicate to said first gating means at the output thereof thatthe sample of information of said speaker A has exceeded saidestablished threshold level and is larger in value than the sample ofinformation of said speaker B; a fourth gating means responsive to theoutputs of said second threshold speaker comparator and said comparisonmeans to indicate to said first gating means at the output thereof thatthe sample of information of said speaker B has exceeded saidestablished threshold level and is larger in value than the sample ofinformation of said speaker A; and a fifth gating means operated inresponse to the outputs of said first gating means and said fourthgating means to operate said output gating means to select and toindicate to said switching system to selection of speaker B, whereby thespeaker B is selected as the active speaker when one or both of thesamples of information of said speakers A and B exceed the establishedthreshold level and the sample of information of said speaker B islarger than the sample of information of said speaker A.
 7. In a pulsecode modulated communication system, as claimed in claim 6, saidconference circuit further comprising delayed time slot address buffermeans coupled to said last frame speaker memory for operating the latterto output the identity of the active speaker during a preceding frame tosaid second gating means.
 8. In a pulse code modulated communicationsystem, as claimed in claim 2, said conference circuit furthercomprising means coupled to the respective ones of said first and secondthreshold speaker comparators for providing a variable threshold level.